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| http://onsemi.com This document, MC74HC4066/D has been canceled and replaced by MC74HC4066A/D LAN was sent 9/28/01 MC54/74HC4066 Quad Analog Switch/ Multiplexer/Demultiplexer High-Performance Silicon-Gate CMOS The MC54/74HC4066 utilizes silicon-gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF-channel leakage current. This bilateral switch/multiplexer/demultiplexer controls analog and digital voltages that may vary across the full power-supply range (from VCC to GND). The HC4066 is identical in pinout to the metal-gate CMOS MC14016 and MC14066. Each device has four independent switches. The device has been designed so that the ON resistances (RON) are much more linear over input voltage than RON of metal-gate CMOS analog switches. This device is identical in both function and pinout to the HC4016. The ON/OFF control inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. For analog switches with voltage-level translators, see the HC4316. * * * * * * * Fast Switching and Propagation Speeds High ON/OFF Output Voltage Ratio Low Crosstalk Between Switches Diode Protection on All Inputs/Outputs Wide Power-Supply Voltage Range (VCC - GND) = 2.0 to 12.0 Volts Analog Input Voltage Range (VCC - GND) = 2.0 to 12.0 Volts Improved Linearity and Lower ON Resistance over Input Voltage than the MC14016 or MC14066 or HC4016 * Low Noise * Chip Complexity: 44 FETs or 11 Equivalent Gates MC54/74HC4066 J SUFFIX CERAMIC PACKAGE CASE 632-08 1 14 14 1 N SUFFIX PLASTIC PACKAGE CASE 646-06 14 1 D SUFFIX SOIC PACKAGE CASE 751A-03 14 1 DT SUFFIX TSSOP PACKAGE CASE 948G-01 ORDERING INFORMATION MC54HCXXXXJ MC74HCXXXXN MC74HCXXXXD MC74HCXXXXDT Ceramic Plastic SOIC TSSOP LOGIC DIAGRAM PIN ASSIGNMENT XA 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC A ON/OFF CONTROL D ON/OFF CONTROL XD YD YC XC XA A ON/OFF CONTROL XB B ON/OFF CONTROL XC C ON/OFF CONTROL XD D ON/OFF CONTROL 1 13 4 5 8 6 11 12 2 YA YA YB XB B ON/OFF CONTROL C ON/OFF CONTROL GND 3 YB ANALOG OUTPUTS/INPUTS 9 YC FUNCTION TABLE On/Off Control Input 10 YD L H State of Analog Switch Off On ANALOG INPUTS/OUTPUTS = XA, XB, XC, XD PIN 14 = VCC PIN 7 = GND MC54/74HC4066 II I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I III I I I I I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIII I I II I I I II I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I II I II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I II I I I I I I I II IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII I I I I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I III I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII MAXIMUM RATINGS* Symbol VCC VIS Vin I Parameter Value Unit V V V Positive DC Supply Voltage (Referenced to GND) Analog Input Voltage (Referenced to GND) Digital Input Voltage (Referenced to GND) DC Current Into or Out of Any Pin - 0.5 to + 14.0 - 0.5 to VCC + 0.5 - 1.5 to VCC + 1.5 25 750 500 450 mA PD Power Dissipation in Still Air, Plastic or Ceramic DIP SOIC Package TSSOP Package Storage Temperature mW Tstg TL - 65 to + 150 260 300 _C _C Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, SOIC or TSSOP Package) (Ceramic DIP) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C Ceramic DIP: - 10 mW/_C from 100_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. I/O pins must be connected to a properly terminated line or bus. IIII I I I III I IIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I I III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIII IIIIIIIIIIIIIIIIIIIIIII III II III I I III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII IIII I III I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII Symbol VCC VIS Vin Parameter Min 2.0 Max Unit V V V V Positive DC Supply Voltage (Referenced to GND) Analog Input Voltage (Referenced to GND) Digital Input Voltage (Referenced to GND) Static or Dynamic Voltage Across Switch 12.0 VCC VCC 1.2 GND GND -- VIO* TA Operating Temperature, All Package Types - 55 0 0 0 0 + 125 1000 500 400 250 _C ns tr, tf Input Rise and Fall Time, ON/OFF Control Inputs (Figure 10) VCC = 2.0 V VCC = 4.5 V VCC = 9.0 V VCC = 12.0 V * For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. RECOMMENDED OPERATING CONDITIONS DC ELECTRICAL CHARACTERISTIC Digital Section (Voltages Referenced to GND) Guaranteed Limit v 85_C 1.5 3.15 6.3 8.4 0.3 0.9 1.8 2.4 Symbol VIH Parameter Test Conditions VCC V - 55 to 25_C 1.5 3.15 6.3 8.4 0.3 0.9 1.8 2.4 v 125_C 1.5 3.15 6.3 8.4 0.3 0.9 1.8 2.4 Unit V Minimum High-Level Voltage ON/OFF Control Inputs Ron = Per Spec 2.0 4.5 9.0 12.0 2.0 4.5 9.0 12.0 VIL Maximum Low-Level Voltage ON/OFF Control Inputs Ron = Per Spec V Iin Maximum Input Leakage Current ON/OFF Control Inputs Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Vin = VCC or GND VIO = 0 V 12.0 0.1 2 8 1.0 20 80 1.0 40 160 A A ICC 6.0 12.0 IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I II I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I II I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I I II I I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I At supply voltage (VCC - GND) approaching 2 V the analog switch-on resistance becomes extremely non-linear. Therefore, for low-voltage operation, it is recommended that these devices only be used to control digital signals. II I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I III I I I I I I II I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I II I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIII I I II I I I II I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I DC ELECTRICAL CHARACTERISTICS Analog Section (Voltages Referenced to GND) AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, ON/OFF Control Inputs: tr = tf = 6 ns) MC54/74HC4066 Symbol Symbol Ron tPLH, tPHL tPZL, tPZH tPLZ, tPHZ Ron CPD Ion Ioff C Maximum On-Channel Leakage Current, Any One Channel Maximum Off-Channel Leakage Current, Any One Channel Maximum Difference in "ON" Resistance Between Any Two Channels in the Same Package Maximum "ON" Resistance Power Dissipation Capacitance (Per Switch) (Figure 13)* Maximum Capacitance Parameter Parameter Vin = VIH VIS = VCC or GND (Figure 4) Vin = VIL VIO = VCC or GND Switch Off (Figure 3) Maximum Propagation Delay, ON/OFF Control to Analog Output (Figures 10 and 1 1) Maximum Propagation Delay, ON/OFF Control to Analog Output (Figures 10 and 11) Maximum Propagation Delay, Analog Input to Analog Output (Figures 8 and 9) Vin = VIH VIS = VCC or GND (Endpoints) IS v 2.0 mA (Figures 1, 2) Vin = VIH VIS = VCC to GND IS v 2.0 mA (Figures 1, 2) Vin = VIH VIS = 1/2 (VCC - GND) IS v 2.0 mA Test Conditions ON/OFF Control Input Control Input = GND Analog I/O Feedthrough 2.0 4.5 9.0 12.0 2.0 4.5 9.0 12.0 2.0 4.5 9.0 12.0 2.0 4.5 9.0 12.0 2.0 4.5 9.0 12.0 12.0 12.0 2.0 4.5 9.0 12.0 VCC V VCC V -- -- -- - 55 to 25_C - 55 to 25_C Typical @ 25C, VCC = 5.0 V 125 25 25 25 150 30 30 30 -- 170 85 85 0.1 0.1 35 1.0 10 50 10 10 10 -- 30 20 20 -- 85 63 63 Guaranteed Limit Guaranteed Limit v 85_C v 85_C 160 32 32 32 190 38 30 30 -- 106 78 78 -- 215 106 106 0.5 0.5 35 1.0 10 65 13 13 13 -- 35 25 25 185 37 37 37 225 45 30 30 -- 130 95 95 -- 255 130 130 1.0 1.0 35 1.0 10 75 15 15 15 -- 40 30 30 15 v 125_C v 125_C Unit Unit A A pF pF ns ns ns MC54/74HC4066 ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted) III I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II II I II II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II III I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIII I II I II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II III I I I II I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I III I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I II I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII Symbol BW Parameter Test Conditions VCC V Limit* 25_C 54/74HC 150 160 160 Unit Maximum On-Channel Bandwidth or Minimum Frequency Response (Figure 5) Off-Channel Feedthrough Isolation (Figure 6) fin = 1 MHz Sine Wave Adjust fin Voltage to Obtain 0 dBm at VOS Increase fin Frequency Until dB Meter Reads - 3 dB RL = 50 , CL = 10 pF fin Sine Wave Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL = 600 , CL = 50 pF fin = 1.0 MHz, RL = 50 , CL = 10 pF 4.5 9.0 12.0 4.5 9.0 12.0 4.5 9.0 12.0 4.5 9.0 12.0 4.5 9.0 12.0 4.5 9.0 12.0 4.5 9.0 12.0 MHz -- - 50 - 50 - 50 - 40 - 40 - 40 60 130 200 30 65 100 dB -- Feedthrough Noise, Control to Switch (Figure 7) Vin v 1 MHz Square Wave (tr = tf = 6 ns) Adjust RL at Setup so that IS = 0 A RL = 600 , CL = 50 pF RL = 10 k, CL = 10 pF mVPP -- Crosstalk Between Any Two Switches (Figure 12) fin Sine Wave Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL = 600 , CL = 50 pF fin = 1.0 MHz, RL = 50 , CL = 10 pF - 70 - 70 - 70 - 80 - 80 - 80 dB THD Total Harmonic Distortion (Figure 14) fin = 1 kHz, RL = 10 k, CL = 50 pF THD = THDMeasured - THDSource VIS = 4.0 VPP sine wave VIS = 8.0 VPP sine wave VIS = 11.0 VPP sine wave % 4.5 9.0 12.0 0.10 0.06 0.04 * Guaranteed limits not tested. Determined by design and verified by qualification. MC54/74HC4066 600 R on , ON RESISTANCE (OHMS) R on , ON RESISTANCE (OHMS) 500 400 300 200 100 0 0 120 100 80 60 40 20 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND 4.5 -55C 125C 25C -55C 25C 125C 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND Figure 1a. Typical On Resistance, VCC = 2.0 V Figure 1b. Typical On Resistance, VCC = 4.5 V 80 R on , ON RESISTANCE (OHMS) R on , ON RESISTANCE (OHMS) 70 60 50 40 30 20 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 25C -55C 125C 120 100 80 60 40 -55C 20 0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND 9.0 125C 25C Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND Figure 1c. Typical On Resistance, VCC = 6.0 V Figure 1d. Typical On Resistance, VCC = 9.0 V 80 R on , ON RESISTANCE (OHMS) 70 60 50 40 30 20 10 0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 11 12 ANALOG IN 125C 25C PROGRAMMABLE POWER SUPPLY + PLOTTER MINI COMPUTER VCC DEVICE UNDER TEST DC ANALYZER -55C COMMON OUT GND Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND Figure 1e. Typical On Resistance, VCC = 12 V Figure 2. On Resistance Test Set-Up MC54/74HC4066 VCC VCC VCC 14 A GND ON N/C GND VCC A OFF 14 VCC 7 SELECTED CONTROL INPUT VIL 7 SELECTED CONTROL INPUT VIH Figure 3. Maximum Off Channel Leakage Current, Any One Channel, Test Set-Up Figure 4. Maximum On Channel Leakage Current, Test Set-Up VCC 14 fin 0.1F ON VOS fin 0.1F VIS OFF RL SELECTED CONTROL INPUT 7 VCC 14 VOS CL* dB METER CL* dB METER 7 SELECTED CONTROL INPUT VCC *Includes all probe and jig capacitance. *Includes all probe and jig capacitance. Figure 5. Maximum On-Channel Bandwidth Test Set-Up Figure 6. Off-Channel Feedthrough Isolation, Test Set-Up VCC/2 14 RL OFF/ON VCC VCC/2 RL IS VOS CL* VCC ANALOG IN tPLH 50% 50% GND tPHL VCC GND Vin 1 MHz tr = tf = 6 ns CONTROL 7 SELECTED CONTROL INPUT ANALOG OUT *Includes all probe and jig capacitance. Figure 7. Feedthrough Noise, ON/OFF Control to Analog Out, Test Set-Up Figure 8. Propagation Delays, Analog In to Analog Out MC54/74HC4066 VCC 14 ANALOG IN ON ANALOG OUT CL* TEST POINT CONTROL 90% 50% 10% tPZL 50% ANALOG OUT 50% *Includes all probe and jig capacitance. tPZH tPHZ 90% tPLZ tr tf VCC GND HIGH IMPEDANCE 10% VOL VOH HIGH IMPEDANCE 7 SELECTED CONTROL INPUT VCC Figure 9. Propagation Delay Test Set-Up Figure 10. Propagation Delay, ON/OFF Control to Analog Out VIS RL 0.1 F TEST POINT OFF RL RL SELECTED CONTROL INPUT 7 VCC/2 CL* RL CL* 14 ON POSITION 1 WHEN TESTING tPHZ AND tPZH 1 2 VCC 1 2 ON/OFF CL* SELECTED CONTROL INPUT 7 POSITION 2 WHEN TESTING tPLZ AND tPZL VCC 14 1 k fin VCC VOS VCC OR GND VCC/2 VCC/2 *Includes all probe and jig capacitance. *Includes all probe and jig capacitance. Figure 11. Propagation Delay Test Set-Up Figure 12. Crosstalk Between Any Two Switches, Test Set-Up VCC A 14 N/C OFF/ON N/C 0.1 F fin ON RL SELECTED CONTROL INPUT VCC/2 7 SELECTED CONTROL INPUT VCC CL* VIS VCC VOS TO DISTORTION METER 7 ON/OFF CONTROL *Includes all probe and jig capacitance. Figure 13. Power Dissipation Capacitance Test Set-Up Figure 14. Total Harmonic Distortion, Test Set-Up MC54/74HC4066 0 -10 -20 -30 dBm -40 -50 -60 -70 -80 -90 1.0 2.0 FREQUENCY (kHz) 3.0 DEVICE SOURCE FUNDAMENTAL FREQUENCY Figure 15. Plot, Harmonic Distortion APPLICATION INFORMATION The ON/OFF Control pins should be at VCC or GND logic levels, VCC being recognized as logic high and GND being recognized as a logic low. Unused analog inputs/outputs may be left floating (not connected). However, it is advisable to tie unused analog inputs and outputs to VCC or GND through a low value resistor. This minimizes crosstalk and feedthrough noise that may be picked-up by the unused I/O pins. The maximum analog voltage swings are determined by the supply voltages VCC and GND. The positive peak analog voltage should not exceed VCC. Similarly, the negative peak analog voltage should not go below GND. In the example below, the difference between VCC and GND is twelve volts. Therefore, using the configuration in Figure 16, a maximum analog signal of twelve volts peak-to-peak can be controlled. When voltage transients above VCC and/or below GND are anticipated on the analog channels, external diodes (Dx) are recommended as shown in Figure 17. These diodes should be small signal, fast turn-on types able to absorb the maximum anticipated current surges during clipping. An alternate method would be to replace the Dx diodes with MOsorbs (high current surge protectors). MOsorbs are fast turn-on devices ideally suited for precise DC protection with no inherent wear out mechanism. VCC = 12 V + 12 V 0V ANALOG I/O 14 ON ANALOG O/I + 12 V 0V Dx VCC 16 ON Dx VCC SELECTED CONTROL INPUT 7 VCC Dx Dx SELECTED CONTROL INPUT 7 OTHER CONTROL INPUTS (VCC OR GND) OTHER CONTROL INPUTS (VCC OR GND) Figure 16. 12 V Application Figure 17. Transient Suppressor Application MC54/74HC4066 +5 V +5 V ANALOG SIGNALS R* R* R* R* 5 6 14 15 R* = 2 TO 10 k 14 ANALOG SIGNALS ANALOG SIGNALS HCT BUFFER 14 ANALOG SIGNALS LSTTL/ NMOS HC4016 LSTTL/ NMOS HC4016 5 6 14 15 CONTROL INPUTS 7 CONTROL INPUTS 7 a. Using Pull-Up Resistors b. Using HCT Buffer Figure 18. LSTTL/NMOS to HCMOS Interface VDD = 5 V VCC = 5 TO 12 V 13 3 5 7 9 11 14 1 16 ANALOG SIGNALS 2 4 6 10 5 6 14 15 14 HC4016 ANALOG SIGNALS MC14504 CONTROL INPUTS 7 8 Figure 19. TTL/NMOS-to-CMOS Level Converter Analog Signal Peak-to-Peak Greater than 5 V (Also see HC4316) CHANNEL 4 1 OF 4 SWITCHES 1 OF 4 SWITCHES COMMON I/O 1 OF 4 SWITCHES 1 OF 4 SWITCHES INPUT 1 OF 4 SWITCHES + 0.01 F 1 2 34 CONTROL INPUTS LF356 OR EQUIVALENT OUTPUT CHANNEL 3 CHANNEL 2 CHANNEL 1 Figure 20. 4-Input Multiplexer Figure 21. Sample/Hold Amplifier MC54/74HC4066 OUTLINE DIMENSIONS J SUFFIX CERAMIC DIP PACKAGE CASE 632-08 ISSUE Y -A14 8 -B1 7 C L NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMESNION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. DIM A B C D F G J K L M N INCHES MIN MAX 0.750 0.785 0.245 0.280 0.155 0.200 0.015 0.020 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0 15 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.94 6.23 7.11 3.94 5.08 0.39 0.50 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0 15 0.51 1.01 -TSEATING PLANE K F G D 14 PL 0.25 (0.010) M N TA S M J 14 PL 0.25 (0.010) M T B S N SUFFIX PLASTIC DIP PACKAGE CASE 646-06 ISSUE L 14 8 NOTES: 1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 4. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M N INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.300 BSC 0_ 10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.62 BSC 0_ 10_ 0.39 1.01 B 1 7 A F C N H G D SEATING PLANE L J K M MC54/74HC4066 OUTLINE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751A-03 ISSUE F -A- 14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. -B- 1 7 P 7 PL 0.25 (0.010) M B M G C R X 45 F SEATING PLANE D 14 PL K M M B S J 0.25 (0.010) T A S DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.75 8.55 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 BSC 0.25 0.19 0.25 0.10 7 0 6.20 5.80 0.50 0.25 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.228 0.244 0.010 0.019 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948G-01 ISSUE O 14X K REF 0.10 (0.004) 0.15 (0.006) T U S M TU S V S N 2X L/2 14 8 0.25 (0.010) M L PIN 1 IDENT. 1 7 B -U- N F DETAIL E K K1 J J1 0.15 (0.006) T U S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ A -V- SECTION N-N -W- C 0.10 (0.004) -T- SEATING PLANE D G H DETAIL E EEE CCC EEE CCC MC54/74HC4066 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada JAPAN: ON Semiconductor, Japan Customer Focus Center 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-0031 Phone: 81-3-5740-2700 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. MC74HC4066/D |
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